View TSXPC603RMABQ6LC_3745202.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

1/40 description the pid7t-603e implementation of powerpc603e (after named 603r) is a low-power implementa- tion of reduced instruction set computer (risc) microprocessors powerpc ? family. the 603r is pin-to-pin compatible with powerpc 603e and 603p in cerquad package. the 603r implements 32-bit effective addresses, integer data types of 8, 16 and 32 bits, and floating-point data types of 32 and 64 bits. the 603r is a low-power design and provides four software controllable power-saving modes. the 603r is a superscalar processor capable of issuing and retiring as many as three instructions per clock. instructions can execute out of order for increased performance ; however, the 603r makes completion appear sequential. the 603r integrates five execution units and is able to exe- cute five instructions in parallel. features 5.6 specint95, 4.0 specfp95 @ 200 mhz (estimated) superscalar (3 instructions per clock peak). dual 16kb caches. selectable bus clock. 32-bit compatibility powerpc implementation. on chip debug support. p d typical = 2.5 watts (200 mhz), full operating conditions. nap, doze and sleep modes for power savings. screening / quality /packaging this product is manufactured in full compliance with: mil-std-883 class q (tbc) or according to tcs standards full military temperature range (t c = -55 c, t c = +125 c) industrial temperature range (t c = -40 c, t c = +110 c) a suffix cerquad 240 ceramic leaded chip carrier cavity up cerquad 240 the 603r provides independent on-chip, 16-kbyte, four-way set-associative, physically addressed caches for instructions and data and on-chip instruction and data memory manage- ment units (mmus). the mmus contain 64-entry, two-way set-associative, data and instruction translation lookaside buffers that provide support for demand-paged virtual memory address translation and variable-sized block translation. the 603r has a selectable 32 or 64-bit data bus and a 32-bit address bus. the 603r interface pro- tocol allows multiple masters to complete for system resources through a central external arbiter. the 603r supports single-beat and burst data transfers for memory accesses, and supports memory-mapped i/o. the 603r uses an advanced, 2.5/3.3-v cmos process technology and maintains full interface compatibility with ttl devices. the 603r integrates in system testability and debugging features through jtag boundary-scan capability. tspc603r in cerquad and mquad packages powerpc 603e tm risc microprocessor family pid7t-603e specification target specification commercial temperature range (t c = 0 c, t c = +70 c) internal // i/o power supply 2.5 5 % // 3.3 v 5 % 240 pin cerquad or 240 pin mquad packages mquad 240 y suffix mquad 240 metal quad flat pack cavity up august 2000
2/40 tspc603r in cerquad and mquad packages summary a. general description 3 . . . . . . . . . . . . . . . . . . . . . 1. introduction 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2. pin assignments 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.1. cerquad and mquad 240 packages 5 . . . . . . . . . . . . 2.2. pinout listing 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3. signal description 8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . b. detailed specifications 11 . . . . . . . . . . . . . . . . . 1. scope 11 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2. applicable documents 11 . . . . . . . . . . . . . . . . . . . . . . . . 3. requirements 11 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.1. general 11 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2. design and construction 11 . . . . . . . . . . . . . . . . . . . . . . . . 3.2.1. terminal connections 11 . . . . . . . . . . . . . . . . . . . . . . 3.2.2. lead material and finish 11 . . . . . . . . . . . . . . . . . . . . . 3.3. absolute maximum ratings 11 . . . . . . . . . . . . . . . . . . . . . . 3.4. recommended operating conditions 12 . . . . . . . . . . . . . 3.5. thermal characteristics 12 . . . . . . . . . . . . . . . . . . . . . . . . . 3.5.1. generalities 12 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.5.2. thermal management example 12 . . . . . . . . . . . . . . 3.6. power consideration 12 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.6.1. dynamic power management 13 . . . . . . . . . . . . . . . . 3.6.2. programmable power modes 13 . . . . . . . . . . . . . . . . 3.6.3. power management modes 13 . . . . . . . . . . . . . . . . . 3.6.4. power management software considerations 15 . . 3.6.5. power dissipation 15 . . . . . . . . . . . . . . . . . . . . . . . . . . 3.7. marking 16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4. electrical characteristics 16 . . . . . . . . . . . . . . . . . . 4.1. general requirements 16 . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.2. static characteristics 16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.3. dynamic characteristics 17 . . . . . . . . . . . . . . . . . . . . . . . . . 4.3.1. clock ac specifications 17 . . . . . . . . . . . . . . . . . . . . . 4.3.2. input ac specifications 18 . . . . . . . . . . . . . . . . . . . . . 4.3.3. output ac specifications 19 . . . . . . . . . . . . . . . . . . . . 4.4. jtag ac timing specifications 21 . . . . . . . . . . . . . . . . . . . 5. functional description 23 . . . . . . . . . . . . . . . . . . . . . . . 5.1. powerpc registers and programming model 23 . . . . . . . 5.1.1. general-purpose registers (gprs) 23 . . . . . . . . . . . 5.1.2. floating-point registers (fprs) 23 . . . . . . . . . . . . . . 5.1.3. condition register (cr) 23 . . . . . . . . . . . . . . . . . . . . . 5.1.4. floating-point status and control register (fpscr) 23 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.1.5. machine state register (msr) 23 . . . . . . . . . . . . . . . 5.1.6. segment registers (srs) 23 . . . . . . . . . . . . . . . . . . . 5.1.7. special-purpose registers (sprs) 23 . . . . . . . . . . . 5.2. instruction set and addressing modes 26 . . . . . . . . . . . . . 5.2.1. powerpc instruction set and addressing modes 26 5.2.2. powerpc 603r microprocessor instruction set 27 . . 5.3. cache implementation 27 . . . . . . . . . . . . . . . . . . . . . . . . . . 5.3.1. powerpc cache characteristics 27 . . . . . . . . . . . . . . 5.3.2. powerpc 603r microprocessor cache implementation 27 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.4. exception model 28 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.4.1. powerpc exception model 28 . . . . . . . . . . . . . . . . . . 5.4.2. powerpc 603r microprocessor exception model 29 5.5. memory management 32 . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5.1. powerpc memory management 32 . . . . . . . . . . . . . 5.5.2. powerpc 603r microprocessor memory management 32 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.6. instruction timing 32 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6. preparation for delivery 33 . . . . . . . . . . . . . . . . . . . . . 6.1. packaging 33 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.2. certificate of compliance 33 . . . . . . . . . . . . . . . . . . . . . . . . 7. handling 33 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8. package mechanical data 33 . . . . . . . . . . . . . . . . . . . . . 8.1. mechanical dimensions of the wire-bond cerquad package 33 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.2. mechanical dimensions of wirebond mquad package 35 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9. clock relationships choice 36 . . . . . . . . . . . . . . . . . . 10. system design information 37 . . . . . . . . . . . . . . . . . . 10.1. pll power supply filtering 37 . . . . . . . . . . . . . . . . . . . . . 10.2. decoupling recommendations 37 . . . . . . . . . . . . . . . . . . 10.3. connection recommendations 37 . . . . . . . . . . . . . . . . . 10.4. pullup resistor requirements 37 . . . . . . . . . . . . . . . . . 11. definitions 38 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12. differences with commercial part 38 . . . . . . . . . 13. ordering information 39 . . . . . . . . . . . . . . . . . . . . . . . .
tspc603r in cerquad and mquad packages 3/40 a. general description completion unit fetch unit dispatch unit branch unit integer unit gen reg unit gen re- name load/ store unit fp re- name fp reg file float unit d mmu 16k data cache i mmu 16k inst. cache bus interface unit system bus 32b address 64b data figure 1 : block diagram
4/40 tspc603r in cerquad and mquad packages 1. introduction the 603r is a low-power implementation of the powerpc microprocessor family of reduced instruction set commuter (risc) micropro - cessors. the 603r implements the 32-bit portion of the powerpc architecture, which provides 32-bit effective addresses, integer data types of 8, 16 and 32 bits, and floating-point data types of 32 and 64 bits. for 64-bit powerpc microprocessors, the powerpc ar chitec- ture provides 64-bit integer data types, 64-bit addressing, and other features required to complete the 64-bit architecture. the 603r provides four software controllable power-saving modes. three of the modes (the nap, doze, and sleep modes) are static in nature, and progressively reduce the amount of power dissipated by the processor. the fourth is a dynamic power management mode that causes the functional units in the 603r to automatically enter a low-power mode when the functional units are idle wi thout affecting operational performance, software execution, or any external hardware. the 603r is a superscalar processor capable of issuing and retiring as many as three instructions per clock. instructions can e xecute out of order for increased performance ; however, the 603r makes completion appear sequential. the 603 e integrates five execution units - an integer unit (iu), a floating-point unit (fpu), a branch processing unit (bpu), a load/store unit (lsu) and a system register unit (sru). the ability to execute five instructions in parallel and the use of simple instruc tions with rapid execution times yield high efficiency and throughput for 603r-based systems. most integer instructions execute in one clo ck cycle. the fpu is pipelined so a single-precision multiply-add instruction can be issued every clock cycle. the 603r provides independent on-chip, 16 kbyte, four-way set-associative, physically addressed caches for instructions and dat a and on-chip instruction and data memory management units (mmus). the mmus contain 64-entry, two-way set-associative, data and instruction translation lookaside buffers (dtlb and itlb) that provide support for demand-paged virtual memory address translation and variable-sized block translation. the tlbs and caches use a least recently used (lru) replacement algorithm. th e 603r also supports block address translation through the use of two independent instruction and data block address translation (ibat and dbat) arrays of four entries each. effective addresses are compared simultaneously with all four entries in the bat array d uring block translation. in accordance with the powerpc architecture, if an effective address hits in both the tlb and bat array, the bat translation takes priority. the 603r has a selectable 32 - or 64-bit - data bus and a 32-bit address bus. the 603r interface protocol allows multiple maste rs to compete for system resources through a central external arbiter. the 603r provides a three-state coherency protocol that suppor ts the exclusive, modified, and invalid cache states. this protocol as a compatible subset of the mesi (modified/exclusive/shared/inva lid) four-state protocol and operates coherently in systems that contain four-state caches. the 603r supports single-beat and burst data transfers for memory accesses, and supports memory-mapped i/o. the 603r uses an advanced, 0.29 m 5 metal layer cmos process technology and maintains full interface compatibility with ttl devices.
tspc603r in cerquad and mquad packages 5/40 2. pin assignments 2.1. cerquad and mquad 240 packages figure 2 : cerquad 240 : top view
6/40 tspc603r in cerquad and mquad packages 2.2. pinout listing table 1.power and ground pins cerquad 240 and mquad 240 packages vcc gnd pll (avdd) 209 internal logic 4, 14, 24, 34, 44, 59, 122, 137, 147, 157, 167, 177, 207 9, 19,29, 39, 49, 65, 116, 132, 142, 152, 162, 172, 182, 206, 239 output drivers 10, 20, 35, 45, 54, 61, 70, 79, 88, 96, 104, 112, 121, 128, 138, 148, 163, 173, 183, 194, 222, 229, 240 8, 18, 33, 43, 53, 60, 69, 77, 86, 95, 103, 111, 120, 127, 136, 146, 161, 171, 181, 193, 220, 228, 238 table 2.signal pinout listing signal name cerquad and mquad pin number a[031] 179, 2, 178, 3, 176, 5, 175, 6, 174, 7, 170, 11, 169, 12, 168, 13, 166, 15, 165, 16, 164, 17, 160, 21, 159, 22, 158, 23, 151, 30, 144, 37 aack 28 abb 36 ap[03] 231,230,227,226 ape 218 artry 32 bg 27 br 219 ci 237 ckstp_in 215 ckstp_out 216 clk_out 221 cse[0-1] 225,150 dbb 145 dbg 26 dbdis 153 dbwo 25 dh[0-31] 115, 114, 113, 110, 109, 108, 99, 98, 97, 94, 93, 92, 91, 90, 89, 87, 85, 84, 83, 82, 81, 80, 78, 76, 75, 74, 73, 72, 71, 68, 67, 66 dl[0-31] 143, 141, 140, 139, 135, 134, 133, 131, 130, 129, 126, 125, 124, 123, 119, 118, 117, 107, 106, 105, 102, 101, 100, 51, 52, 55, 56, 57, 58, 62, 63, 64 dp[0-7] 38, 40, 41, 42, 46, 47, 48, 50 dpe 217 drtry 156 gbl 1 hreset 214 int 188 l1_tstclk 1 204 l2_tstclk 1 203 lssd_mode 1 205
tspc603r in cerquad and mquad packages 7/40 signal name cerquad and mquad pin number mcp 186 pll_cfg[0-3] 213, 211, 210, 208 qack 235 qreq 31 rsrv 232 smi 187 sreset 189 sysclk 212 ta 155 tben 234 tbst 192 tc[01] 224, 223 tck 201 tdi 199 tdo 198 tea 154 tlbisync 233 tms 200 trst 202 ts 149 tsiz[0-2] 197, 196, 195 tt[0-4] 191, 190, 185, 184, 180 wt 236 nc notes : 1. these are test signals for factory use only and must be pulled up to vdd for normal machine operation. 2. ovdd inputs supply power to the i/o drivers and vdd inputs supply power to the processor core. future members of the 603 fami ly may use different ovdd and vdd input levels.
8/40 tspc603r in cerquad and mquad packages 3. signal description figure 3, aucun lien and aucun lien describe the signals on the tspc603r and indicate signal functions. the test signals, trst , tms, tck, tdi and tdo, comply with subset p-1149.1 of the ieee testability bus standard. the 3 signals lssd_mode , li_tstclk and l2_tstclk are test signals for factory use only and must be pulled up to vdd for normal machine operations. br bg abb ts tt[0-4] ap[0-3] ape tbst tsiz[0-2] gbl ci wt cse[0-1] tc[0-1] aack artry sysclk clk_out pll_cfg[0-3] dbg dbwo dbb dpe dp[0-7] dh[0-31], dl[0-31] a[0-31] dbdis ta drtry tea int , smi mcp hreset , sreset ckstp_in , ckstp_out rsrv qreq , qack tben tlbisync trst , tck, tms, tdi, td0 5 lssd_mode , l1_tstclk, l2_tstclk 3 1 1 1 vdd ovdd gnd avdd address arbitration address start address bus transfer attribute address termination clocks data attribution data transfer data termination interrupts checkstops reset processor status jtag/cop interface lssd test control power supply 64 8 1 1 1 1 1 2 1 2 2 1 2 1 1 20 19 40 1 1 1 1 1 1 1 32 4 1 5 3 1 1 1 2 4 1 2 1 1 603r voltdetgnd 1 power supply indicator figure 3 : functional signal groups table 3.address and data bus signal index signal name mnemonic signal function signal type address bus a[0-31] if output, physical address of data to be transferred. if input, represents the physical address of a snoop operation. i/o data bus dh[0-31] represents the state of data, during a data write operation if output, or during a data read operation if input. i/o data bus dl[0-31] represents the state of data, during a data write operation if output, or during a data read operation if input. i/o
tspc603r in cerquad and mquad packages 9/40 table 4.signal index signal name mnemonic signal function signal type address acknowledge aack the address phase of a transaction is complete input address bus busy abb if output, the 603r is the address bus master if input, the address bus is in use i/o address bus parity ap[0-3] if output, represents odd parity for each of 4 bytes of the physical address for a transaction if input, represents odd parity for each of 4 bytes of the physical address for snooping operations i/o address parity error ape incorrect address bus parity detected on a snoop output address retry artry if output, detects a condition in which a snooped address tenure must be retried if input, must retry the preceding address tenure i/o bus grant bg may, with the proper qualification, assume mastership of the address bus input bus request br request mastership of the address bus output cache inhibit cl a single-beat transfer will not be cached output test clock clk_out provides pll clock output for pll testing and monitoring output checkstop input ckstp_in must terminate operation by internally gating off all clocks, and release all outputs input checkstop output ckstp_out has detected a checkstop condition and has ceased operation output cache set entry cse[0-1] cache replacement set element for the current transaction reloading into or writing out of the cache output data bus busy dbb if output, the 603r is the data bus master if input, another device is bus master i/o data bus disable dbdis (for a write transaction) must release data bus and the data bus parity to high impedance during the following cycle input data bus grant dbg may, with the proper qualification, assume mastership of the data bus input data bus write only dbw0 may run the data bus tenure input data bus parity dp[0-7] if output, odd parity for each of 8 bytes of data write transactions if input, odd parity for each byte of read data i/o data parity error dpe incorrect data bus parity output data retry drtry must invalidate the data from the previous read operation input global gbl if output, a transaction is global if input, a transaction must be snooped by the 603r i/o hard reset hreset initiates a complete hard reset operation input interrupt int initiates an interrupt if bit ee of msr register is set input lssd_mode lssd test control signal for factory use only input l1_tstclk lssd test control signal for factory use only input l2_tstclk lssd test control signal for factory use only input machine check inter- rupt mcp initiates a machine check interrupt operation if the bit me of msr regis- ter and bit emcp of hid0 register are set input
10/40 tspc603r in cerquad and mquad packages signal name signal type signal function mnemonic pll configuration pll_cfg[0-3] configures the operation of the pll and the internal processor clock frequency input quiescent acknowledge qack all bus activity has terminated and the 603r may enter a quiescent (or low power) state input quiescent request qreq is requesting all bus activity normally to enter a quiescent (low power) state output reservation rsrv represents the state of the reservation coherency bit in the reservation address register output system management interrupt smi initiates a system management interrupt operation if the bit ee of msr register is set input soft reset sreset initiates processing for a reset exception input system clock sysclk represents the primary clock input for the 603r, and the bus clock fre- quency for 603r bus operation input transfer acknowledge ta a single-beat data transfer completed successfully or a data beat in a burst transfer completed successfully input timebase enable tben the timebase should continue clocking input transfer burst tbst if output, a burst transfer is in progress if input, when snooping for single-beat reads i/o transfer code tc[0-1] special encoding for the transfer in progress output test clock tck clock signal for the ieee p1149.1 test access port (tap) input test data input tdi serial data input for the tap input test data output tdo serial data output for the tap output transfer error acknowledge tea a bus error occurred input tlbi sync tlbisync instruction execution should stop after execution of a tlbsync instruction input test mode select tms selects the principal operations of the test-support circuitry input test reset trst provides an asynchronous reset of the tap controller input transfer size tsiz[0-2] for memory accesses, these signals along with tbst indicate the data transfer size for the current bus operation i/o transfer start ts if output, begun a memory bus transaction and the address bus and transfer attribute signals are valid if input, another master has begun a bus transaction and the address bus and transfer attribute signals are valid for snooping (see gbl ) i/o transfer type tt[0-4] type of transfer in progress i/o write-through wt a single-beat transaction is write-through output power supply indicator voltdetgnd available only on bga package indicates to the power supply that a lowvoltage processor is present. output
tspc603r in cerquad and mquad packages 11/40 b. detailed specifications 1. scope this drawing describes the specific requirements for the microprocessor tspc603r, in compliance with mil-std-883 class b or tcs standard screening. 2. applicable documents 1) mil-std-883 : test methods and procedures for electronics. 2) mil-prf-38535 : general specifications for microcircuits. 3. requirements 3.1. general the microcircuits are in accordance with the applicable documents and as specified herein. 3.2. design and construction 3.2.1. terminal connections the terminal connections shall be is shown in figure 15 ( b. detailed specifications) and figure 3 ( a. general description). 3.2.2. lead material and finish lead material and finish shall be as specified in mil-std-1835 (see enclosed 8) 3.3. absolute maximum ratings absolute maximum ratings are stress rating only and functional operation at the maximum is not guaranteed. stresses beyond thos e listed may affect device reliability or cause permanent damage to the device table 5.absolute maximum rating for the 603r parameter symbol min max unit core supply voltage v dd -0.3 2.75 v pll supply voltage av dd -0.3 2.75 v i/o supply voltage ov dd -0.3 3.6 v input voltage v in -0.3 5.5 v storage temperature range t stg -55 +150 c notes: 1. functional operating conditions are given in ac and dc electrical specifications. stresses beyond the absolute maximums lis ted may affect device reliability or cause permanent damage to the device. 2. caution : input voltage must not be greater than ovdd by more than 2.5 v at any times, including during power-on reset. 3. caution : ovdd voltage must not be greater than vdd/avdd by more than 1.2 v at any times, including during power-on reset. 4. caution : vdd/avdd voltage must not be greater than ovdd by more than 0.4 v at any times, including during power-on reset.
12/40 tspc603r in cerquad and mquad packages 3.4. recommended operating conditions these are the recommended and tested operating conditions. proper device operation outside of these conditions is not guarantee d. parameter symbol min max unit core supply voltage v dd 2.375 2.625 v pll supply voltage av dd 2.375 2.625 v i/o supply voltage ov dd 3.135 3.465 v input voltage v in gnd 5.5 v case operating temperature t c -55 +125 c junction operating temperature t j +135 c 3.5. thermal characteristics this section provides thermal management data for the 603r ; this information is based on a typical desktop configuration using a 240 lead, wire-bond cerquad and mquad packages with cavity up (silicon die is attached on the bottom of the package). this configu - ration allows to dissipate through the pcb. 3.5.1.generalities the thermal characteristics for a wire-bond cerquad package are as follows : thermal resistance (junction-to-bottom of the case) (typical)= r jc or jc = 2.5 c/watt. thermal resistance (junction-to-top of the case) is typically 25 c/w. the thermal characteristics for the mquad package is : thermal resistance (junction-to-bottom of the case) (typical) = r jc or jc = 1.3 c/watt. 3.5.2.thermal management example the following example is based on a typical desktop configuration using a wire-bond package with cavity up (see 3.5.1). the junction temperature can be calculated from the junction to ambient thermal resistance, as follows : junction temperature : t j = t c + r jc * p t j = t a + (r cs + r sa ) * p + r jc * p so t j = t a + (r jc + r cs + r sa ) * p where : t a is the ambient temperature in the vicinity of the device r ja is the junction-to-ambient thermal resistance r jc is the junction-to-case thermal resistance of the device r cs is the case-to-heat sink thermal resistance of the interface material r sa is the heat sink-to-ambient thermal resistance p is the power dissipated by the device because of the dissipation is made through the pcb, r cs and r sa are user values, and can vary considerably regarding the customer application. in a typical customer application, if r cs is 0.5 c/w, r sa is 3 c/w and ta is 110 c, tj can be estimated. tj = 110 c + (2.5 + 0.5 +3) x 2.5 = 125 c. note that verification of external thermal resistance and case temperature should be performed for each application. thermal re sist- ance can vary considerably due to many factors including degree of air turbulence. 3.6. power consideration the powerpc603r is a microprocessor specifically designed for low-power operation. as the 603e microprocessor version, the 603r provides both automatic and program-controllable power reduction modes for progressive reduction of power consumption. this chapter describes the hardware support provided by the 603r for power management.
tspc603r in cerquad and mquad packages 13/40 3.6.1. dynamic power management dynamic power management automatically powers up and down the individual execution units of the 603r, based upon the contents of the instruction stream. for example, if no floating-point instructions are being executed, the floating-point unit is automa tically pow- ered down. power is not actually removed from the execution unit ; instead, each execution unit has an independent clock input, which is automatically controlled on a clock-by- clock basis. since cmos circuits consume negligible power when they are not switchin g, stopping the clock to an execution unit effectively eliminates its power consumption. the operation of dpm is completely transp arent to software or any external hardware. dynamic power management is enabled by setting bit 11 in hid0 on power-up, of following hreset . 3.6.2. programmable power modes the 603r provides four programmable power states - full power, doze, nap and sleep. software selects these modes by setting one (and only one) of the three power saving mode bits. hardware can enable a power management state through external asynchronous interrupts the hardware interrupt causes the transfer of program flow to interrupt handler code. the appropriate mode is then s et by the software. the 603r provides a separate interrupt and interrupt vector for power management - the system management interrup t (smi). the 603r also contains a decrement timer which allows it to enter the nap or doze mode for a predetermined amount of tim e and then return to full power operation through the decrementer interrupt (di). note that the 603r cannot switch from on power mana ge- ment mode to another without first returning to full on mode. the nap and sleep modes disable bus snooping ; therefore, a hardw are handshake is provided to ensure coherency before the 603r enters these power management modes. aucun lien summarizes the four power states. table 6.power pc 603r microprocessor programmable power modes pm mode functioning units activation method full-power wake up method full power all units active full power (with dpm) requested logic by demand by instruction dispatch doze - bus snooping - data cache as needed - decrementer timer controlled by sw external asynchronous exceptions* decrementer interrupt reset nap decrementer timer controlled by hardware and software external asynchronous exceptions decrementer interrupt reset sleep none controlled by hardware and software external asynchronous exceptions reset * exceptions are referred to as interrupts in the architecture specification 3.6.3. power management modes the following sections describe the characteristics of the 603r's power management modes, the requirements for entering and exi ting the various modes, and the system capabilities provided by the 603r while the power management modes are active. 1. full-power mode with dpm disabled full-power mode with dpm disabled power mode is selected when the dpm enable bit (bit 11) in hid0 is cleared. - default state following power-up and hreset . - all functional units are operating at full processor speed at all times. 2. full-power mode with dpm enabled full-power mode with dpm enabled (hid0[11] = 1) provides on-chip power management without affecting the functionality or perfor - mance of the 603r. - required functional units are operating at full processor speed. - functional units are clocked only when needed. - no software or hardware intervention required after mode is set. - software/hardware and performance transparent. 3. doze mode doze ode disables most functional units but maintains cache coherency by enabling the bus interface unit and snooping. a snoop hit will cause the 603r to enable the data cache, copy the data back to memory, disable the cache, and fully return to the doze sta te.
14/40 tspc603r in cerquad and mquad packages most functional units disabled. bus snooping and time base/decrementer still enabled. dose mode sequence : - set doze bit (hid0[8) = 1). - 603r enters doze mode after several processor clocks. several methods of returning to full-power mode : - assert int , smi , mcp or decrementer interrupts. - assert hard reset or soft reset. transition to full-power state takes no more than a few processor cycles. pll running and locked to sysclk. 4. nap mode the nap mode disables the 603r but still maintains the phase locked loop (pll) and the time base/decrementer. the time base can be used to restore the 603r to full-on state after a programmed amount of time. because bus snooping is disabled for nap and sleep mode, a hardware handshake using the quiesce request (qreq ) and quiesce acknowledge (qack ) signals are requires to maintain data coherency. the 603r will assert the qreq signal to indicate that it is ready to disable bus snooping. when the system has ensured that snooping is no longer necessary, it will assert qack and the 603r will enter the sleep or nap mode. time base/decrementer still enabled. most functional units disabled (including bus snooping). all nonessential input receivers disables. nap mode sequence : - set nap bit (hid0[9] = 1). - 603r asserts quiesce request (qreq ) signal. - system asserts quiesce acknowledge (qack ) signal. - 603r enters sleep mode after several processor clocks. several methods of returning to full-power mode : - assert int , spi , mcp or decrementer interrupts. - assert hard reset or soft reset. transition to full-power takes no more than a few processor cycles. pll running and locked to sysclk. 5. sleep mode sleep mode consumes the least amount of power of the four modes since all functional units are disabled. to conserve the maximu m amount of power, the pll may be disabled and the sysclk may be removed. due to the fully static design of the 603r, internal pr oc- essor state is preserved when no internal clock is present. because the time base and decrementer are disabled while the 603r i s in sleep mode, the 603r's time base contents will have to be updated from an external time base following sleep mode if accurate t ime-of- day maintenance is required. before the 603r enters the sleep mode, the 603r will assert the qreq signal to indicate that it is ready to disable bus snooping. when the system has ensured that snooping is no longer necessary, it will assert qack and the 603r will enter the sleep mode. all functional units disabled (including bus snooping and time base). all nonessential input receivers disabled : - internal clock regenerators disabled. - pll still running (see below). sleep mode sequence : - set sleep bit (hid0[10] = 1). - 603r asserts quiesce request (qreq ). - system asserts quiesce acknowledge (qack ). - 603r enters sleep mode after several processor clocks. several methods of returning to full-power mode : - assert int , smi , or mcp interrupts. - assert hard reset or soft reset.
tspc603r in cerquad and mquad packages 15/40 pll may be disabled and sysclk may be removed while in sleep mode. return to full-power mode after pll and sysclk disabled in sleep mode : - enable sysclk. - reconfigure pll into desired processor clock mode. - system logic waits for pll startup and relock time (100 sec). - system logic asserts one of the sleep recovery signals (for example, int or smi). 3.6.4. power management software considerations since the 603r is a dual issue processor with out -of-order execution capability, care must be taken in how the power managemen t mode is entered. furthermore, nap and sleep modes require all outstanding bus operations to be completed before the power man- agement mode is entered. normally during system configuration time, one of the power management modes would be selected by setting the appropriate hid0 mode bit. later on, the power management mode is invoked by setting the msr[pow] bit. to provide a clean transition into and out of the power management mode, the stmsr [pow] should be preceded by a sync instruction and followed by an isync instruction. 3.6.5. power dissipation table 7.power dissipation vdd/avdd = 2.5 5 % v dc, ovdd = 3.3 5 % v dc, gnd = 0 v dc, 0 c t c 125 c cpu clock frequency 166 mhz 200 mhz units full-on mode (dpm enabled) typical 2.1 2.5 w max 3.2 4.0 w doze mode typical 1.5 1.7 w nap mode typical 100 120 mw sleep mode typical 96 110 mw sleep mode-pll disabled typical 60 60 mw sleep mode-pll and sysclk disabled typical 25 25 mw maximum 60 60 mw notes: 1 these values apply for all valid pll_cfg[03] settings and do not include output driver power (ovdd) or analog supply power (a vdd). ovdd power is system dependent but is typically 10% of vdd. worstcase avdd = 15 mw. 2 typical power is an average value measured at vdd=avdd=2.5 v, ovv=3.3 v, in a system executing typical applications and benchm ark sequences. 3 maximum power is measured at vdd=2.625 v using a worstcase instruction mix. 4 to calculate the power consumption at low temperature (55 c), use a factor of 1.25 .
16/40 tspc603r in cerquad and mquad packages 3.7. marking the document where are defined the marking are identified in the related reference documents. each microcircuit are legible and permanently marked with the following information as minimum : - thomson logo, - manufacturer's part number, - class b identification if applicable, - date-code of inspection lot, - esd identifier if available, - country of manufacturing. 4. electrical characteristics 4.1. general requirements all static and dynamic electrical characteristics specified for inspection purposes and the relevant measurement conditions are given below : - table 8 : static electrical characteristics for the electrical variants. - tables 9, 10 and 11 : dynamic electrical characteristics for the 603r. these specifications are for 166 mhz to 200 mhz processor core frequencies. the processor core frequency is determined by the bus (sysclk) frequency and the settings of the pll_cfg0 to pll_cfg3 signals. all timings are specified respective to the rise edge of sysclk. 4.2. static characteristics table 8.electrical characteristics vdd = avdd = 2.5 v 5 % ; ovdd = 3.3 5 % v dc, gnd = 0 v dc, 55 c t c 125 c characteristics symbol min max unit input high voltage (all inputs except sysclk) v ih 2.0 5.5 v input low voltage (all inputs except sysclk) v il gnd 0.8 v sysclk input high voltage cv ih 2.4 5.5 v sysclk input low voltage cv il gnd 0.4 v input leakage current v in = 3.465 v (1, 3) i in - 30 a v in = 5.5 v (1, 3) i in - 300 a hi-z (off-state) v in = 3.465 v (1, 3) leakage current i tsi - 30 a v in = 5.5 v (1, 3) i tsi - 300 a output high voltage i oh = 7 ma v oh 2.4 - v output low voltage i ol = +7 ma v ol - 0.4 v capacitance, v in = 0 v, f = 1 mhz (2) (excludes ts , abb , dbb , and artry ) c in - 10.0 pf capacitance, v in = 0 v, f = 1 mhz (2) (for ts , abb , dbb , and artry ) c in - 15.0 pf notes: 1. excludes test signals (lssd_mode, l1_tstclk, l2_tstclk, and jtag signals). 2. capacitance is periodically sampled rather than 100 % tested. 3. leakage currents are measured for nominal ovdd and vdd or both ovdd and vdd. same variation (for example, both vdd and ovdd vary by either +5 % or 5 %).
tspc603r in cerquad and mquad packages 17/40 4.3. dynamic characteristics 4.3.1. clock ac specifications table 9 provides the clock ac timing specifications as defined in figure 4. table 9.clock ac timing specifications vdd = avdd = 2.5 v 5 % ; ovdd = 3.3 5 % v dc, gnd = 0 v dc, 55 c t c 125 c num characteristics 166 mhz 200 mhz unit note min max min max processor frequency 150 166 150 200 mhz 5 vco frequency 300 332 300 400 mhz 5 sysclk (bus) frequency 25 66.7 33.3 66.7 mhz 5 1 sysclk cycle time 15 30 13.3 30 ns 2,3 sysclk rise and fall time 2.0 2.0 ns 1 4 sysclk duty cycle (1.4v mea- sured) 40.0 60.0 40.0 60.0 % 3 sysclk jitter 150 150 ps 2 603r internal pll relock time 100 100 s 3,4 notes : 1. rise and fall times for the sysclk input are measured from 0.4 v to 2.4 v. 2. cycle-to-cycle jitter is guaranteed by design. 3. timing is guaranteed by design and characterization, and is not tested. 4. pll relock time is the maximum amount of time required for pll lock after a stable vdd, ovdd, avdd and sysclk are reached dur ing the power-on reset sequence. this specification also applies when the pll has been disabled and subsequently re-enabled during slee p mode. also note that hreset must be held asserted for a minimum of 255 bus clocks after the pll relock time (100 s) during the power-on reset sequence. 5. caution : the sysclk frequency and pll_cfg[03] settings must be chosen such that the resulting sysclk (bus) frequency, cpu (core) frequency, and pll (vco) frequency do not exceed their respective maximum or minimum operating frequencies. refer to the pll_cf g[03] signal description for valid pll_cfg[03] settings. figure 4 : sysclk input timing diagram
18/40 tspc603r in cerquad and mquad packages 4.3.2. input ac specifications table 10 provides the input ac timing specifications for the 603r as defined in figure 5 and figure 6. table 10.input ac timing specifications vdd = avdd = 2.5 v 5 % ; ovdd = 3.3 5 % v dc, gnd = 0 v dc, 55 c t c 125 c num characteristics 166,200 mhz unit note min max 10a address/data/transfer attribute inputs valid to sysclk (input setup) 2.5 - ns 2 10b all other inputs valid to sysclk (input setup) 4.0 - ns 3 10c mode select inputs valid to hreset (input setup) (for drtry , qack and tlbisync ) 8 - t sysclk 4,5,6,7 11a sysclk to address/data/transfer attribute inputs invalid (input hold) 1.0 - ns 2 11b sysclk to all other inputs invalid (input hold) 1.0 - ns 3 11c hreset to mode select inputs invalid (input hold) (for drtry , qack , and tlbisync ) 0 - ns 4,6,7 notes : 1. all input specifications are measured from the ttl level (0.8 or 2.0 v) of the signal in question to the 1.4 v of the rising edge of the input sysclk. both input and output timings are measured at the pin. see figure 6. 2. address/data/transfer attribute input signals are composed of the following: a[031], ap[03], tt[04], tc[01], tbst , tsiz[02], gbl , dh[031], dl[031], dp[97]. 3. all other input signals are composed of the following: ts , abb , dbb , artry , bg , aack , dbg , dbwo , ta , drtry , tea , dbdis , hreset , sreset , int , smi , mcp , tben, qack , tlbisync . 4. the setup and hold time is with respect to the rising edge of hreset . see figure 6. 5. t sysclk is the period of the external clock (sysclk) in nanoseconds (ns). the numbers given in the table must be multiplied by the per iod of sysclk to compute the actual time duration (in nanoseconds) of the parameter in question. 6. these values are guaranteed by design, and are not tested. 7. this specification is for configuration mode only. also note that hreset must be held asserted for a minimum of 255 bus clocks after the pll relock time (100 s) during the power-on reset sequence. figure 5 : input timing diagram
tspc603r in cerquad and mquad packages 19/40 figure 6 : mode select input timing diagram 4.3.3. output ac specifications table 11 provides the output ac timing specifications for the 603r (shown in figure 7). table 11.output ac timing specifications vdd = avdd = 2.5 v 5 % ; ovdd = 3.3 5 % v dc, gnd = 0 v dc, c l = 50 pf, 55 c t c 125 c num characteristic 166,200 mhz unit note min max 12 sysclk to output driven (output enable time) 1.0 ns 13a sysclk to output valid (5.5 v to 0.8 v ts , abb , artry , dbb ) 9.0 ns 4 13b sysclk to output valid (ts , abb , artry , dbb ) 8.0 ns 6 14a sysclk to output valid (5.5 v to 0.8 v all except ts , abb , artry , dbb ) 11.0 ns 4 14b sysclk to output valid (all except ts ,abb ,artry ,dbb ) 9.0 ns 6 15 sysclk to output invalid (output hold) 1.0 ns 3 16 sysclk to output high impedance (all except artry , abb , dbb ) 8.5 ns 17 sysclk to abb , dbb , high impedance after precharge 1.0 t sysclk 5, 7 18 sysclk to artry high impedance before precharge 8.0 ns 19 sysclk to artry precharge enable 0.2 * t sysclk + 1.0 ns 3, 5, 8 20 maximum delay to artry precharge 1.0 t sysclk 5, 8 21 sysclk to artry high impedance after precharge 2.0 t sysclk 6, 8 notes :1 all output specifications are measured from the 1.4 v of the rising edge of sysclk to the ttl level (0.8 v or 2.0 v) of the s ignal in question. both input and output timings are measured at the pin. see figure 7. 2. all maximum timing specifications assume c l = 50 pf. 3. this minimum parameter assumes c l = 0 pf. 4. sysclk to output valid (5.5 v to 0.8 v) includes the extra delay associated with discharging the external voltage from 5.5 v to 0.8 v instead of from vdd to 0.8 v (5 v cmos levels instead of 3.3 v cmos levels). 5. t sysclk is the period of the external bus clock (sysclk) in nanoseconds (ns). the numbers given in the table must be multiplied by the period of sysclk to compute the actual time duration (in nanoseconds) of the parameter in question. 6. output signal transitions from gnd to 2.0 v or vdd to 0.8 v. 7. nominal precharge width for abb and dbb is 0.5 * t sysclk . 8. nominal precharge width for artry is 1.0 * t sysclk .
20/40 tspc603r in cerquad and mquad packages figure 7 : output timing diagram
tspc603r in cerquad and mquad packages 21/40 4.4. jtag ac timing specifications table 12.jtag ac timing specifications (independent of sysclk) vdd = avdd = 2.5 v 5 % ; ovdd = 3.3 5 % v dc, gnd = 0 v dc, c l = 50 pf, 55 c t c 125 c figure 8 : clock input timing diagram figure 9 : trst timing diagram
22/40 tspc603r in cerquad and mquad packages figure 10 : boundary-scan timing diagram figure 11 : test access port timing diagram
tspc603r in cerquad and mquad packages 23/40 5. functional description 5.1. powerpc registers and programming model the powerpc architecture defines register-to-register operations for most computational instructions. source operands for these instructions are accessed from the registers or are provided as immediate values embedded in the instruction opcode. the three- reg- ister instruction format allows specification of a target register distinct from the two source operands. load and store instru ctions transfer data between registers and memory. powerpc processors have two levels of privilege - supervisor mode of operation (typically used by the operating system) and use r mode of operation (used by the application software). the programming models incorporate 32 gprs, 32 fprs, special-purpose registers (sprs) and several miscellaneous registers. each powerpc microprocessor also has its own unique set of hardware imple - mentation (hid) registers. having access to privilege instructions, registers, and other resources allows the operating system to control the application environ- ment (providing virtual memory and protecting operating-system and critical machine resources). instructions that control the s tate of the processor, the address translation mechanism, and supervisor registers can be executed only when the processor is operating in supervisor mode. the following sections summarize the powerpc registers that are implemented in the 603r. 5.1.1. general-purpose registers (gprs) the powerpc architecture defines 32 user-level, general-purpose registers (gprs). these registers are either 32 bits wide in 32 -bit powerpc microprocessors and 64 bits wide in 64-bit powerpc microprocessors. the gprs serve as the data source or destination for all integer instructions. 5.1.2. floating-point registers (fprs) the powerpc architecture also defines 32 user-level, 64-bit floating-point registers (fprs). the fprs serve as the data source or destination for floating-point instructions. these registers can contain data objects of either single - or double - precision floating-point formats. 5.1.3. condition register (cr) the cr is a 32-bit user-level register that consists of eight four-bit fields that reflect the results of certain operations, s uch as move, integer and floating-point compare, arithmetic, and logical instructions, and provide a mechanism for testing and branching. 5.1.4. floating-point status and control register (fpscr) the floating-point status and control register (fpscr) is a user-level register that contains all exception signal bits, except ion sum- mary bits, exception enable bits, and rounding control bits needed for compliance with the ieee 754 standard. 5.1.5. machine state register (msr) the machine state register (msr) is a supervisor-level register that defines the state of the processor. the contents of this r egister are saved when an exception is taken and restored when the exception handling completes. the 603r implements the msr as a 32-bit register, 64-bit powerpc processors implement a 64-bit msr. 5.1.6. segment registers (srs) for memory management, 32-bit powerpc microprocessors implement sixteen 32-bit segment registers (srs). to speed access, the 603r implements the segment registers as two arrays ; a main array (for data memory accesses) and a shadow array (for instr uc- tion memory accesses). loading a segment entry with the move to segment register (stsr) instruction loads both arrays. 5.1.7. special-purpose registers (sprs) the powerpc operating environment architecture defines numerous special-purpose registers that serve a variety of functions, su ch as providing controls, indicating status, configuring the processor, and performing special operations. during normal execution , a program can access the registers, shown in figure 12, depending on the program's access privilege (supervisor or user, determin ed by the privilege-level (pr) bit in the msr). note that register such as the gprs and fprs are accessed through operands that ar e part of the instructions. access to registers can be explicit (that is, through the use of specific instructions for that purpose su ch as move to special-purpose register (mtspr) and move from special-purpose register (mfspr) instructions) or implicit, as the part of the e xecu- tion of an instruction. some registers are accessed both explicitly and implicitly. il the 603r, all sprs are 32 bits wide.
24/40 tspc603r in cerquad and mquad packages user-level sprs the following 603r sprs are accessible by user-level software : link register (lr) - the link register can be used to provide the branch target address and to hold the return address after br anch and link instructions. the lr is 32 bits wide in 32-bit implementations. count register (ctr) - the crt is decremented and tested automatically as a result of branch-and-count instructions. the ctr is 32 bits wide in 32-bit implementations. integer exception register (xer) - the 32-bit xer contains the summary overflow bit, integer carry bit, overflow bit, and a fie ld specifying the number of bytes to be transferred by a load string word indexed (lswx) or store string word indexed (stswx) instruction. supervisor-level sprs the 603r also contains sprs that can be accessed only by supervisor-level software. these registers consist of the following : the 32-bit dsisr defines the cause of data access and alignment exceptions. the data address register (dar) is a 32-bit register that holds the address of an access after an alignment or dsi exception. decrementer register (dec) is a 32-bit decrementing counter that provides a mechanism for causing a decrementer exception after a programmable delay. the 32-bit sdr1 specifies the page table format used in virtual-to-physical address translation for pages. (note that physical address is referred to as real address in the architecture specification). the machine status save/restore register 0 (srr0) is a 32-bit register that is used by the 603r for saving the address of the i nstruc- tion that caused the exception, and the address to return to when a return from interrupt ( rfi ) instruction is executed. the machine status save/restore register 1 (srr1) is a 32-bit register used to save machine status on exceptions and to restore machine status when an rfi instruction is executed. the 32-bit sprg0-sprg3 registers are provided for operating system use. the external access register (ear) is a 32-bit register that controls access to the external control facility through the exter nal con- trol in word indexed ( eciwx ) and external control out word indexed ( ecowx ) instructions. the time base register (tb) is a 64-bit register that maintains the time of day and operates interval timers. the tb consists o f two 32-bit fields - time base upper (tbu) and time base lower (tbl). the processor version register (pvr) is a 32-bit, read-only register that identifies the version (model) and revision level of the pow- erpc processor. block address translation (bat) arrays - the powerpc architecture defines 16 bat registers, divided into four pairs of data bat s (dbats) and four pairs of instruction bats (ibats). see figure 12 for a list of the spr numbers for the bat arrays. the following supervisor-level sprs are implementation-specific to the 603r : the dmiss and imiss registers are read-only registers that are loaded automatically upon an instruction or data tlb miss. the hash1 and hash2 registers contain the physical addresses of the primary and secondary page table entry groups (ptegs). the icmp and dcmp registers contain a duplicate of the first word in the page table entry (pte) for which the table search is l ook- ing. the required physical address (rpa) register is loaded by the processor with the second word of the correct pte during a page table search. the hardware implementation (hid0 and hid1) registers provide the means for enabling the 603ros checkstops and features, and allows software to read the configuration of the pll configuration signals. the instruction address breakpoint register (iabr) is loaded with an instruction address that is compared to instruction addres ses in the dispatch queue. when an address match occurs, an instruction address breakpoint exception is generated. figure 13 shows all the 603r registers available at the user and supervisor level. the number to the right of the sprs indicate the number that is used in the syntax of the instruction operands to access the register.
tspc603r in cerquad and mquad packages 25/40 (1) these registers are 603r-specific registers. they may not be supported by other powerpc processors. figure 12 : powerpc microprocessor programming model register
26/40 tspc603r in cerquad and mquad packages 5.2. instruction set and addressing modes the following subsections describe the powerpc instruction set and addressing modes in general. 5.2.1. powerpc instruction set and addressing modes all powerpc instructions are encoded as single-word (32-bit) opcodes. instruction formats are consistent among all instruction types, permitting efficient decoding to occur in parallel with operand accesses. this fixed instruction length and consistent format g reatly simplifies instruction pipelining. powerpc instruction set the powerpc instructions are divided into the following categories : integer instructions - these include computational and logical instructions. - integer arithmetic instructions. - integer compare instructions. - integer logical instructions. - integer rotate and shift instructions. floating-point instructions -these include floating-point computational instructions, as well as instructions that affect the fpscr. - floating-point arithmetic instructions. - floating-point multiply/add instructions. - floating-point rounding and conversion instructions. - floating-point compare instructions. - floating-point status and control instructions. load/store instructions - these include integer and floating-point load and store instructions. - integer load and store instruction. - integer load and store multiple instructions. - floating-point load and store. - primitives used to construct atomic memory operations ( lwarx and stwcx. instructions). flow control instructions - these include branching instructions, condition register logical instructions, trap instructions, and other instructions that affect the instruction flow. - branch and trap instructions. - condition register logical instructions. processor control instructions - these instructions are used for synchronizing memory accesses and management of caches, tlbs, and the segment registers. - move to/from spr instructions. - move to/from msr. - synchronize. - instruction synchronize. memory control instruction - these instructions provide control of caches, tlbs, and segment registers. - supervisor-level cache management instructions. - user-level cache instructions. - segment register manipulation instructions. - translation lookaside buffer management instructions. note that this grouping of the instructions does not indicate which execution unit executes a particular instruction or group o f instruc- tions. integer instructions operate on byte, half-word, and word operands. floating-point instructions operate on single-precision (on e word) and double-precision (one double word) floating-point operands. the powerpc architecture uses instructions that are four bytes long and word-aligned. it provides for byte, half-word, and word operand loads and stores between memory and a set of 32 gprs. it al so provides for word and double-word operand loads and stores between memory and a set of 32 floating-point registers (fprs). computational instructions do not modify memory. to use a memory operand in a computation and then modify the same or another memory location, the memory contents must be loaded into a register, modified, and then written back to the target location wit h dis- tinct instructions. powerpc processors follow the program flow when they are in the normal execution state. however, the flow of instructions can b e interrupted directly by the execution of an instruction or by an asynchronous event. either kind of exception may cause one of several components of the system software to be invoked.
tspc603r in cerquad and mquad packages 27/40 calculating effective addresses the effective address (ea) is the 32-bit address computed by the processor when executing a memory access or branch instruction or when fetching the next sequential instruction. the powerpc architecture supports two simple memory addressing modes : ea = (ra|0) + offset (including offset = 0) (register indirect with immediate index). ea = (ra|0) + rb (register indirect with index). these simple addressing modes allow efficient address generation for memory accesses. calculation of the effective address for aligned transfers occurs in a single clock cycle. for a memory access instruction, if the sum of the effective address and the operand length exceeds the maximum effective addre ss, the memory operand is considered to wrap around from the maximum effective address to effective address 0. effective address computations for both data and instruction accesses use 32-bit unsigned binary arithmetic. a carry from bit 0 is ignored in 32-bit implementations. 5.2.2. powerpc 603r microprocessor instruction set the 603r instruction set is defined as follows : the 603r provides hardware support for all 32-bit powerpc instructions. the 603r provides two implementation-specific instructions used for software table search operations following tlb misses : - load data tlb entry ( tlbld ). - load instruction tlb entry ( tlbli ). the 603r implements the following instructions which are defined as optional by the powerpc architecture : - external control in word indexed ( eciwx ). - external control out word indexed ( ecowx ). - floating select ( fsed ). - floating reciprocal estimate single-precision ( fres ). - floating reciprocal square root estimate ( frsqrte ). - store floating-point as integer word ( stfiwx ). 5.3. cache implementation the following subsections describe the powerpc architecture's treatment of cache in general, and the 603r specific implementati on, respectively. 5.3.1. powerpc cache characteristics the powerpc architecture does not define hardware aspects of cache implementations. for example, some powerpc processors, including the 603r, have separate instruction and data caches (hardware architecture), while others, such as the powerpc 601 ? microprocessor, implement a unified cache. powerpc microprocessor control the following memory access modes on a page or block basis : write-back/write-through mode. cache-inhibited mode. memory coherency. note that in the 603r, a cache line is defined as eight words. the vea defines cache management instructions that provide a mea ns by which the application programmer can affect the cache contents. 5.3.2. powerpc 603r microprocessor cache implementation the 603r has two 16-kbyte, four-way set-associative (instruction and data) caches. the caches are physically addressed, and the data cache can operate in either write-back or write-through mode as specified by the powerpc architecture. the data cache is configured as 128 sets of 4 lines each. each line consists of 32 bytes, two state bits, and an address tag. t he two state bits implement the three-state mei (modified/exclusive/invalid) protocol. each line contains eight 32-bit words. note tha t the powerpc architecture defines the term block as the cacheable unit. for the 603r, the block size is equivalent to a cache line. a block diagram of the data cache organization is shown in figure 13. the instruction cache also consists of 128 sets of 4 lines, and each line consists of 32 bytes, an address tag, and a valid bit . the instruction cache may not be written to except through a line fill operation. the instruction cache is not snooped, and cache c oherency must be maintained by software. a fast hardware invalidation capability is provided to support cache maintenance. the organizat ion of the instruction cache is very similar to the data cache shown in figure 13. each cache line contains eight contiguous words from memory that are loaded from an 8-word boundary (that is, bits a27-a32 of t he effective addresses are zero) ; thus, a cache line never crosses a page boundary. misaligned accesses across a page boundary ca n incur a performance penalty.
28/40 tspc603r in cerquad and mquad packages the 603's cache lines are loaded in four beats of 64 bits each. the burst load is performed as ocritical double word firsto. th e cache that is being loaded is blocked to internal accesses until the load completes. the critical double word is simultaneously written to the cache and forwarded to the requesting unit, thus minimizing stalls due to load delays. to ensure coherency among caches in a multiprocessor (or multiple caching-device) implementation, the 603r implements the mei protocol. these three states, modified, exclusive, and invalid, indicate the state of the cache block as follows : modified - the cache line is modified with respect to system memory ; that is, data for this address is valid only in the cache and not in system memory. exclusive - this cache line holds valid data that is identical to the data at this address in system memory. no other cache has this data. invalid - this cache line does not hold valid data. cache coherency is enforced by on-chip bus snooping logic. since the 603r's data cache tags are single ported, a simultaneous l oad or store and snoop access represent a resource contention. the snoop access is given first access to the tags. the load or stor e then occurs on the clock following snoop. figure 13 : data cache organization 5.4. exception model the following subsections describe the powerpc exception model and the 603r implementation, respectively. 5.4.1. powerpc exception model the powerpc exception mechanism allows the processor to change to supervisor state as a result of external singles, errors, or unusual conditions arising in the execution of instructions, and differ from the arithmetic exceptions defined by the ieee for floating- point operations. when exceptions occur, information about the state of the processor is saved to certain registers and the pro cessor begins execution at an address (exception vector) predetermined for each exception. processing of exceptions occurs in supervis or mode. although multiple exception conditions can map to a single exception vector, a more specific condition may be determined by exa min- ing a register associated with the exception - for example, the dsisr and the fpscr. additionally, some exception conditions ca n be explicitly enable or disabled by software. the powerpc architecture requires that exceptions be handled in program order ; therefore, although a particular implementation may recognize exception conditions out of order, they are presented strictly in order. when an instruction-caused exception is recog- nized, any unexecuted instructions that appear earlier in the instruction stream, including any that have not yet entered the e xecute state, are required to complete before the exception is taken. any exceptions caused by those instructions are handled first. l ikewise, exceptions that are asynchronous and precise are recognized when they occur, but are not handled until the instruction currentl y in the completion state successfully completes execution or generates an exception, and the completed store queue is emptied. unless a catastrophic causes a system reset or machine check exception, only one exception is handled at a time. if, for exampl e, a single instruction encounters multiple exception conditions, those conditions are encountered sequentially. after the exception han- dler handles an exception, the instruction execution continues until the next exception condition is encountered. however, in m any cases there is no attempt to re-execute the instruction. this method of recognizing and handling exception conditions sequentia lly guarantees that exceptions are recoverable. exception handlers should save the information stored in srr0 and srr1 early to prevent the program state from being lost due t o a system reset and machine check exception or to an instruction-caused exception in the exception handler, and before enabling ex ter- nal interrupts.
tspc603r in cerquad and mquad packages 29/40 the powerpc architecture support four types of exceptions : synchronous, precise - these are causes by instructions. all instruction-caused exceptions are handled precisely ; that is, the machine state at the time the exception occurs is known and can be completely restored. this means that (excluding the trap and system call exceptions) the address of the faulting instruction is provided to the exception handler and that neither the fault ing instruction nor subsequent instructions in the code stream will complete execution before the exception is taken. once the exce p- tion is processed, execution resumes at the address of the faulting instruction (or at an alternate address provided by the exc eption handler). when an exception is taken due to an trap or system call instruction, execution resumes at an address provided by the handler. synchronous, imprecise - the powerpc architecture defines two imprecise floating-point exception modes, recoverable and nonrecoverable. even though the 603r provides a means to enable he imprecise modes, it implements these modes identically to the precise mode (-hat is, all enabled floating-point enabled exceptions are always precise on the 603r). asynchronous, maskable - the external, smi, and decrementer interrupts are maskable asynchronous exceptions. when these exceptions occur, their handling is postponed until the next instruction, and any exceptions associated with that instruction, com- pletes execution. if there are no instructions in the execution units, the exception is taken immediately upon determination of the correct restart address (for loading srr0). asynchronous, non maskable - there are two non maskable asynchronous exceptions: system reset and the machine check exception. these exceptions may not be recoverable, or may provide a limited degree of recoverability. all exceptions report recoverability through the smr[ri] bit. 5.4.2. powerpc 603r microprocessor exception model a specified by the powerpc architecture, all 603r exceptions can be described as either precise or imprecise and either synchro nous or asynchronous. asynchronous exceptions (some or which are maskable) are caused by events external to the processor's execu- tion ; synchronous exceptions, which are all handled precisely by the 603r, are caused by instructions. the 603r exception clas ses are shown in table 13. synchronous/asynchronous precise/imprecise exception type asynchronous, non maskable imprecise machine check system reset asynchronous, maskable precise external interrupt decrementer system management interrupt synchronous precise instruction-caused exceptions table 13.powerpc 603r microprocessor exception classifications although exceptions have other characteristics as well, such as whether they are maskable or non maskable, the distinctions sho wn in table 13 define categories of exceptions that the 603r handles uniquely. note that table 13 includes no synchronous imprecis e instructions. while the powerpc architecture supports imprecise handling of floating-point exceptions, the 603r implements thes e exception modes as precise exceptions. the 603r's exceptions, and conditions that cause them, are listed in table 14. exceptions that are specific to the 603r are ind icated.
30/40 tspc603r in cerquad and mquad packages table 14.exceptions and conditions
tspc603r in cerquad and mquad packages 31/40
32/40 tspc603r in cerquad and mquad packages 5.5. memory management the following subsections describe the memory management features of the powerpc architecture, and the 603r implementation, respectively. 5.5.1. powerpc memory management the primary functions of the mmu are to translate logical (effective) addresses to physical addresses for memory accesses, and to provide access protection on blocks and pages of memory. there are two types of accesses generated by the 603r that require address translation - instruction accesses, and data accesse s to memory generated by load and store instructions. the powerpc mmu and exception model support demand-paged virtual memory. virtual memory management permits execution of programs larger than the size of physical memory ; demand-paged implies that individual pages are loaded into physical memory from system memory only when they are first accessed by an executing program. the hashed page table is a variable-sized data structure that defines the mapping between virtual page numbers and physical pag e numbers. the page table size is a power of 2, and its starting address is a multiple of its size. the page table contains a number of page table entry groups (ptegs). a pteg contains eight page table entries (ptes) of eight bytes each ; therefore, each pteg is 64 bytes long. pteg addresses are entry points for table search operations. address translations are enabled by setting bits in the msr-msr[ir] enables instruction address translations and msr[dr] enable s data address translations. 5.5.2. powerpc 603r microprocessor memory management the instruction and data memory management units in the 603r provide 4 gbyte of logical address space accessible to supervisor and user programs with a 4-kbyte page size and 256-mbyte segment size. block sizes range from 128 kbyte to 256mbyte and are software selectable. in addition, the 603r uses an interim 52-bit virtual address and hashed page tables for generating 32-bit physical addresses. the mmus in the 603r rely on the exception processing mechanism for the implementation of the paged virtual memory environment and for enforcing protection of designated memory areas. instruction and data tlbs provide address translation in parallel with the on-chip cache access, incurring no additional time p enalty in the event of a tlb hit. a tlb is a cache of the most recently used page table entries. software is responsible for maintaining the consistency of the tlb with memory. the 603r's tlbs are 64-entry, two-way set-associative caches that contain instruction and d ata address translations. the 603r provides hardware assist for software table search operations through the ashed page table on tl b misses. supervisor software can invalidate tlb entries selectively. the 603r also provides independent four-entry bat arrays for instructions and data that maintain address translations for block s of memory. these entries define blocks that can vary from 128 kbyte to 256 mbyte. the bat arrays are maintained by system software . as specified by the powerpc architecture, the hashed page table is a variable-sized data structure that defines the mapping bet ween virtual page numbers and physical page numbers. the page table size is a power of 2, and its starting address is a multiple of its size. also as specified by the powerpc architecture, the page table contains a number of page table entry groups (ptegs). a pteg con- tains eight page table entries (ptes) of eight bytes each ; therefore, each pteg is 64 bytes long. pteg addresses are entry poi nts for table search operations. 5.6. instruction timing the 603r is a pipelined superscalar processor. a pipelined processor is one in which the processing of an instruction is reduce d into discrete stages. because the processing of an instruction is broken into a series of stages, an instruction does not require th e entire resources of an execution unit. for example, after an instruction completes the decode stage, it can pass on to the next stage, while the subsequent instruction can advance into the decode stage. this improves the throughput of the instruction flow.
tspc603r in cerquad and mquad packages 33/40 for example, it may take three cycles for a floating-point instruction to complete, but if there are no stalls in the floating- point pipeline, a series of floating-point instructions can have a throughput of one instruction per cycle. the instruction pipeline in the 603r has four major pipeline stages, described a follows : the fetch pipeline stage primarily involves retrieving instructions from the memory system and determining the location of the next instruction fetch. additionally, the bpu decodes branches during the fetch stage and folds out branch instructions before the d is- patch stage if possible. the dispatch pipeline stage is responsible for decoding the instructions supplied by the instruction fetch stage, and determini ng which of the instructions are eligible to be dispatched in the current cycle. in addition, the source operands of the instructi ons are read from the appropriate register file and dispatched with the instruction to the execute pipeline stage. at the end of the di spatch pipeline stage, the dispatched instructions and their operands are latched by the appropriate execution unit. during the execute pipeline stage each execution unit that has an executable instruction executes the selected instruction (per - haps over multiple cycles), writes the instruction's result into the appropriate rename register, and notifies the completion s tage that the instruction has finished execution. in the case of an internal exception, the execution unit reports the exception to the completion/writeback pipeline stage and discontinues instruction execution until the exception is handled. the exception is not signaled until that instruction is the next to be completed. execution of most floating-point instructions is pipelined within the fpu allowing up to three instructions to be executing in the fpu concurrently. the pipeline stages for the floating-point unit are multiply, add, and round-convert. execution of most load/store instructions is also pipelined. the load/store units has two pipeline stag es. the first stage is for effective address calculation and mmu translation and the second stage is for accessing the data in the cache. the complete/writeback pipeline stage maintains the correct architectural machine state and transfers the contents of the renam e registers to the gprs and fprs as instructions are retired. if the completion logic detects an instruction causing an exception , all following instructions are cancelled, their execution results in rename registers are discarded, and instructions are fetch ed from the correct instruction stream. a superscalar processor is one that issues multiple independent instructions into multiple pipelines allowing instructions to e xecute in parallel. the 603r has five independent execution units, one each for integer instructions, floating-point instructions, branch instruc- tions, load/store instructions, and system register instructions. the iu and the fpu each have dedicated register files for mai ntaining operands (gprs and fprs, respectively), allowing integer calculations and floating-point calculations to occur simultaneously w ith- out interference. because the powerpc architecture can be applied to such a wide variety of implementations, instruction timing among various pow - erpc processors varies accordingly. 6. preparation for delivery 6.1. packaging microcircuits are prepared for delivery in accordance with mil-prf-38535. 6.2. certificate of compliance tcs offers a certificate of compliances with each shipment of parts, affirming the products are in compliance either with mil-s td-883 and guarantying the parameters not tested at temperature extremes for the entire temperature range. 7. handling mos devices must be handled with certain precautions to avoid damage due to accumulation of static charge. input protection devices have been designed in the chip to minimize the effect of this static buildup. however, the following handling practices are recommended : a) devices should be handled on benches with conductive and grounded surfaces. b) ground test equipment, tools and operator. c) do not handle devices by the leads. d) store devices in conductive foam or carriers. e) avoid use of plastic, rubber, or silk in mos areas. f) maintain relative humidity above 50 percent if practical. 8. package mechanical data 8.1. mechanical dimensions of the wire-bond cerquad package
34/40 tspc603r in cerquad and mquad packages millimeters dim min typ max a 30.86 31.00 31.75 b 30.86 31.00 31.75 c 3.67 3.95 4.15 d 0.185 0.220 0.270 e 3.10 3.50 3.90 f 0.175 0.200 0.225 g 0.50 bsc he 2.025 2.100 2.175 j 0.130 0.147 0.175 k 0.45 0.50 0.55 p 0.25 bsc s 34.41 34.58 34.75 u 17.20 17.30 17.40 v 34.41 34.58 34.75 w 0.25 0.50 0.75 y 17.20 17.30 17.40 z 0.122 0.127 0.132 aa 1.80 ref ab 0.95 ref 21 4 7 notes : 1. dimensioning and tolerancing per asme y14.5m1994 2. controlling dimension : millimeter. 3. datum plane h is located at bottom of lead and is coincident with the lead where the lead exits the ceramic body at the bottom of the parting line. 4. datum l. m and n to be determined at datum plane h. 5. dimension s and v to be determined at seating plane t. 6. dimension a and b define maximum ceramic body dimensions including glass protrusion and top and bottom mismatch. top wire bonds ceramic body alloy 42 leads die
tspc603r in cerquad and mquad packages 35/40 8.2. mechanical dimensions of wirebond mquad package
36/40 tspc603r in cerquad and mquad packages 9. clock relationships choice the 603r microprocessors offer customers numerous clocking options. an internal phase-lock loop synchronizes the processor (cpu) clock to the bus or system clock (sysclk) at various ratios. inside each powerpc microprocessor is a phase-lock loop circuit. a voltage controlled oscillator (vco) is precisely controlled in fre- quency and phase by a frequency/phase detector which compares the input bus frequency (sysclk frequency) to a submultiple of the vco. the ratio of cpu to sysclk frequencies is often referred to as the bus mode (for example, 2:1 bus mode). in the table 15, the horizontal scale represents the bus frequency (sysclk) and the vertical scale represents the pllcfg[03] signals. for a given sysclk (bus) frequency, the pll configuration signals set the internal cpu and vco frequency of operation. table 15.cpu frequencies for common bus frequencies and multipliers pll_cfg[03] cpu frequency in mhz (vco frequency in mhz) busto core multiplier coreto vco multiplier bus 25 mhz bus 33.33 mhz bus 40 mhz bus 50 mhz bus 60 mhz bus 66.67 mhz 0100 2x 2x 0101 2x 4x 0110 2.5x 2x 150 (300) 166 (333) 1000 3x 2x 150 (300) 180 (360) 200 (400) 1110 3.5x 2x 175 (350) 1010 4x 2x 160 (320) 200 (400) 0111 4.5x 2x 150 (300) 180 (360) 1011 5x 2x 166 (333) 200 (400) 1001 5.5x 2x 183 (366) 1101 6x 2x 150 (300) 200 (400) 0011 pll bypass 1111 clock off notes : 1. some pll configurations may select bus, cpu or vco frequencies which are not supported 2. in pllbypass mode, the sysclk input signal clocks the internal processor directly, the pll is disabled, and the bus mode is set for 1:1 mode operation. this mode is intended for factory use only. note : the ac timing specifications given in this document do not apply in pllbypass mode. 3. in clockoff mode, no clocking occurs inside the 603r regardless of the sysclk input.
tspc603r in cerquad and mquad packages 37/40 10. system design information 10.1. pll power supply filtering the avdd power signal is provided on the 603e to provide power to the clock generation phaselocked loop. to ensure stability o f the internal clock, the power supplied to the avdd input signal should be filtered using a circuit similar to the one shown in figu re 17. the circuit should be placed as close to the avdd pin to ensure it filters out as much noise as possible. the 0.1 f capacitor should be closest to the avdd pin, followed by the 10 f capacitor, and finally the 10 resistor to vdd. these traces should be kept short and direct. vdd avdd 0.1 f f gnd 10 figure 14 : pll power supply filter circuit 10.2. decoupling recommendations due to the 603e's dynamic power management feature, large address and data buses, and high operating frequencies, the 603e can generate transient power surges and high frequency noise in its power supply, especially while driving large capacitive loads. this noise must be prevented from reaching other components in the 603e system, and the 603e itself requires a clean, tightly regula ted source of power. therefore, it is recommended that the system designer place at least one decoupling capacitor at each vdd and ovdd pin of the 603e. it is also recommended that these decoupling capacitors receive their power from separate vdd, ovdd, and gnd power planes in the pcb, utilizing short traces to minimize inductance. these capacitors should vary in value from 220 pf to 10 f to provide both highand lowfrequency filtering, and should be placed as close as possible to their associated vdd or ovdd pin. suggested values for the vdd pins 220 pf (ceramic), 0,01 f (ceramic) and 0,1 f (ceramic). suggested values for the ovdd pins 0,01 f (ceramic), 0,1 f (ceramic), and 10 f (tantalum). only smt (surface mount technology) capacitors should be used to minimize lead inductance. in addition, it is recommended that there be several bulk storage capacitors distributed around the pcb, feeding the vdd and ov dd planes, to enable quick recharging of the smaller chip capacitors. these bulk capacitors should also have a low esr (equivalent series resistance) rating to ensure the quick response time necessary. they should also be connected to the power and ground planes through two vias to minimize inductance. suggested bulk capacitors 100 f (avx tps tantalum) or 330 f (avx tps tanta- lum). 10.3. connection recommendations to ensure reliable operation, it is highly recommended to connect unused inputs to an appropriate signal level. unused active l ow inputs should be tied to vdd. unused active high inputs should be connected to gnd. all nc (noconnect) signals must remain unconnected. power and ground connections must be made to all external vdd, ovdd, and gnd pins of the 603e. 10.4. pullup resistor requirements the 603e requires highresistive (weak : 10 k ) pullup resistors on several control signals of the bus interface to maintain the con- trol signals in the negated state after they have been actively negated and released by the 603e or other bus master. these sig nals are ts , abb , dbb , and artry . in addition, the 603e has three opendrain style outputs that require pullup resistors (weak or stronger : 4.7 k 10 k if they are used by the system. these signals are ape , dpe , and ckstp _out . during inactive periods on the bus, the address and transfer attributes on the bus are not driven by any master and may float i n the highimpedance state for relatively long periods of time. since the 603e must continually monitor these signals for snooping, t his float condition may cause excessive power draw by the input revivers on the 603e. it is recommended that these signals be pulled up trough weak (10 k ) pullup resistors or restored in some manner by the system. the snooped address and transfer attribute inputs are a ? 03], ap[03], tt[04], tbst , and gbl . the data bus input receivers are normally turned off when no read operation is in progress and do not require pullup resistors on the data bus.
38/40 tspc603r in cerquad and mquad packages 11. definitions datasheet status validity objective specification this datasheet contains target and goal specifi- cation for discussion with customer and applica- tion validation. before design phase. target specification this datasheet contains target or goal specifica- tion for product development. valid during the design phase. preliminary specification site this datasheet contains preliminary data. addi- tional data may be published later ; could include simulation result. valid before characteriza- tion phase. preliminary specification site this datasheet contains also characterization results. valid before the industrial- ization phase. product specification this datasheet contains final product specifica- tion. valid for production pur- pose. limiting values limiting values given are in accordance with the absolute maximum rating system (iec 134). stress above one or more of the limiting values may cause permanent damage to the device. these are stress ratings only and operation of the device at these or at any other conditions above those given in the characteristics sections of the specification is not implied. exposure to limiting values for extended periods may affect device reliability. application information where application information is given, it is advisory and does not form part of the specification. life support applications these products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. tcs customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify tcs for any damages resulting from such improper use or sale. 12. differences with commercial part commercial part military part package tbga cerquad and mquad temperature range tj = 0 to 105c tc = -55c to +125c power consumption use a 1.25 factor to calculate at low temperature (-55c)
tspc603r in cerquad and mquad packages 39/40 13. ordering information temperature range : t c screening leve l (1) : package : ts pc603r m a 8 m : 55, +125 c v : 40, +110 c c : 0, +70 c b /q a : cerquad y : mquad l bus divider (to be confirmed) l : any bus 66 mhz max internal processor speed (1) 6 :166 mhz 8 : 200 mhz 10 : 233 mhz (tbd) 12 : 266 mhz (tbd) (1) for availability of the different versions, contact your atmel sale office __ : standard b/q : mil-std-883, class q (tbc) b/t : according to mil-std-883 type (c ) revision level (tsxpc603r if prototype) information furnished is believed to be accurate and reliable. however atmel-grenoble assumes no responsibility for the conse- quences of use of such information nor for any infringement of patents or other rights of third parties which may result from i ts use. no license is granted by implication or otherwise under any patent or patent rights of atmel-grenoble. specifications mentioned in this publication are subject to change without notice. this publication supersedes and replaces all information previously supplied. atmel- grenoble products are not authorized for use as critical components in life support devices or systems without express written approval from atmel-grenoble. ? 2000 atmel-grenoble- printed in france - all rights reserved. this product is manufactured by atmel-grenoble- 38521 saint-egreve - france. for further information please contact : atmel-grenoble - route dpartementale 128 - b.p. 46 - 91401 orsay cedex - france - phone +33 (0)1 69 33 00 00 - fax +33 (0)1 69 33 03 21. internet:http://www.atmel-grenoble.com
40/40 tspc603r in cerquad and mquad packages

▲Up To Search▲

Price & Availability of TSXPC603RMABQ6LC

	To Download TSXPC603RMABQ6LC Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .